1. Field of the Invention
The present invention relates to a configuration of a semiconductor memory device having a redundancy function.
2. Description of the Background Art
A conventional semiconductor memory device is generally pre-provided with a redundant portion in a memory cell array in order to compensate yield reduction due to occurrence of a defection in a memory cell included in the memory cell array.
FIG. 11 schematically illustrates a configuration of such a conventional memory cell array.
Referring to FIG. 11, memory cell array 100 includes a normal memory cell array portion 100n and a redundant memory cell array portion 100R.
Redundant memory cell array portion 100R includes a redundant memory cell row portion 100RR, a redundant memory cell column portion 100RC, and a redundant part of the redundant portions 100RRC.
The memory cell space of normal memory cell array portion 100n is tested during a manufacturing process of the semiconductor memory device to detect a defective memory cell. The detected defective memory cell is replaced by a memory cell in redundant memory cell array portion 100R.
A method for performing such replacement generally includes programming of a defective address corresponding to the defective memory cell using a fuse circuit. The programming of such a defective address is performed by blowing off a fuse using electricity, laser or the like.
Further, a defective memory cell may exist in the memory space for redundant memory cell array portion 100R. Therefore, the test for the memory cell space during the manufacturing process, as described above, also needs to perform a test for redundant memory cell array portion 100R.
FIG. 12 is a schematic block diagram for illustrating the configuration of memory cell array 100 shown in FIG. 11 in more detail.
Referring to FIG. 12, normal memory cell array portion 100n is provided with word lines WL0 to WL15 corresponding to the memory cell rows thereof, whereas redundant memory cell row portion 1O0RR is provided with spare word lines SWL0 to SWL3 corresponding to the memory cell rows thereof. Word lines WL0 to WL15 are selectively activated by a row decoder 110 decoding a row address signal.
A spare row decoder 112xe2x80x2 provided corresponding to spare word lines SWL0 to SWL3 performs non-volatile storage of a defective row address which includes a defective memory cell by a fuse element or the like, and when the defective row address is accessed, activates one of spare word lines SWL0 to SWL3, for example, spare word line SWL2, instead of a word line WLn corresponding to the defective row address.
Further, bit line pairs BL0 and /BL0 to BL15 and /BL15 are provided in common to normal memory cell array portion 100n and redundant memory cell row portion 100RR, corresponding to the memory cell rows thereof. Spare bit line pairs SBL0 and /SBL0 to SBL3 and /SBL3 are provided in redundant memory cell column portion 100RC, corresponding to the memory cell columns thereof. A memory cell MC is provided corresponding to each crossing point of bit line pairs BL0, /BL0 to BL15, /BL15 and spare bit lines SBL0, /SBL0 to SBL3, /SBL3, and word lines WL0 to WL15 and spare word lines SWL0 to SWL3.
Column decoder 120 decodes a column address signal, and selectively activates a sense amplifier and I/O circuit (hereinafter referred to as SA+I/O circuit) 140 for a selected memory cell column, to selectively transmit data read onto a bit line pair corresponding to the selected memory cell column to IO line pairs IO and /IO.
It is noted, in FIG. 12, that SA+I/O circuit 140 includes a differential amplifier for amplifying a potential difference of a bit line pair and a gate circuit for selectively connecting the selected bit line pair and IO line pair IO, /IO.
Spare column decoder 122xe2x80x2 stores a defective column address including a defective memory cell, by a fuse element or the like, and when the defective column address is accessed, selectively connects one of the spare bit line pairs, for example, spare bit line pair SBL0 and /SBL0, to IO line pair IO and /IO, instead of a bit line pair corresponding to the defective column address, for example, a bit line pair BL12 and /BL12.
A testing operation for detecting a defective memory cell for the semiconductor memory device having memory cell array 100 as shown in FIG. 12 will now be described.
The test for the memory cell space constituted by the conventional memory cell array 100 as shown in FIG. 12 includes a plurality of types of tests as described below.
(1) The test before a replacement process by a redundant portion includes the following:
(1-1) A test for normal memory cell array portion 100n in the memory cell space;
(1-2) A test for redundant memory cell array portion 100R in the memory cell space.
(2) The test after the replacement process by the redundant portion includes the following:
(2-1) A test for a normal portion (including an address replaced by the redundant portion) in the memory cell space.
Referring to FIG. 12, the test for the normal memory cell array portion in the memory cell space described above performed before the replacement process by the redundant portion (1-1) includes a test for the memory cell space corresponding to word lines WL0 to WL15 and bit line pairs BL0, /BL to BL15, /BL15.
The test for the redundant memory cell array portion in the memory cell space performed before the replacement process by the redundant portion (1-2) includes tests for three portions as described below.
i) A test for the memory cell space constituted by spare word lines SWL0 to SWL3 and bit line pairs BL0, /BL0 to BL15, /BL15;
ii) A test for the memory cell space constituted by word lines WL0 to WL15 and spare bit line pairs SBL0, /SBL0 to SBL3, /SBL3; and
iii) A test for the memory, cell space constituted by spare word lines SWL0 to SWL3, and spare bit line pairs SBL0, /SBL0 to SBL3, /SBL3.
If redundant memory cell array portions 100RR and 100RC include a defective bit as a result of such tests for the redundancy memory cell array portions, a repair is performed by replacing the defective portion with redundant part of the redundant portions 100RRC. In such a case, it is unnecessary to completely repair redundant portions 100RR and 100RC, and it would be sufficient if there are replaceable spare rows or columns of at least a number required for repairing the defective bit of the normal memory cell array portion.
Further, in the test performed after the replacement process by the redundant memory cell array portion (2-1) when, for example, word line WLn is replaced by a spare word line SWL2, a test for the memory cell space constitute by word lines W10 to WLnxe2x88x921, SWL2, WLn+1 to WL15, and bit line pairs BL0, /BL0 to BL15,/BL15 will be performed.
In the memory cell space, the boundaries of the normal memory cell array portion and the redundant memory cell array portion are physically adjacent to each other. Thus, the configurations thereof are basically the same, except for what is used for driving the portions, row decoder 110 and column decoder 120 or redundant row decoder 112xe2x80x2 and redundant column decoder 122xe2x80x2.
In other words, they are different in the respect that an address provided upon access of the memory cell array is allocated to normal memory cell array portion 100n, whereas no address is allocated to redundant memory cell array portion 100R since this portion is for replacing a memory cell row or a memory cell column in normal memory cell array portion 100n. 
If, for example, word line WLn is replaced with spare word line SWL2 as described above, a defective memory cell existing in a memory cell row corresponding to word line WLn will be repaired.
However, malfunction of a defective memory cell MCf1 corresponding to word line WLn is sometimes caused by an interference (e.g., weak leakage) or the like between the defective memory cell MCf1 and memory cell MCf2 adjacent to defective memory cell MCf1 and corresponding to the neighboring word line WLnxe2x88x921. In such a case, defective memory cell MCf1 can be repaired by replacing word line WLn with spare word line SWL2.
However, in a subsequent acceleration test, word line WLn will not be selected during the acceleration test inspite of the fact that no replacement was made to word line WLnxe2x88x921 including memory cell MCf2 having the interference with defective memory cell MCf1. Thus, it will be difficult to accelerate and elicit the influence of the interference existing between such memory cells (MCf1, MCf2).
In other words, because of the replacement made by the redundant memory cell row, the defection to be elicited may possibly remain concealed in the subsequent acceleration test.
A case where a memory to be replaced is adjacent to a defective memory cell may have a problem similar to the one described above.
Further, even when no redundant memory cell array portion is used, if a defective memory cell exists in redundant memory cell array portion 100R adjacent to normal memory cell array portion 100n, the redundant memory cell array portion will not be selected as well by the acceleration test, and thus such defection may not be elicited by the acceleration test.
It is possible to improve the yield of a semiconductor memory device by providing redundant memory cell array portion 100R corresponding to normal memory cell array portion 100n as described above. However, nowadays, such simple yield improvement is insufficient, since a defective mode may be concealed, due to interference existing between memory cells or the like, as a device structure is being smaller in size.
In such a case, even if the defective memory cell is simply replaced by a redundant memory cell, it will rather be difficult to elicit a defection by the acceleration test.
Further, if such a defective mode difficult for the acceleration test were to be elicited, it would require an extended test time.
It is an object of the present invention to provide a semiconductor memory device enabling an elicitation of a concealed defective mode existing between memory cells by an acceleration test, even when a defective memory cell existing in a normal memory cell array portion is replaced by a memory cell in a redundant memory cell array portion.
According to one aspect of the present invention, a semiconductor memory device includes a memory cell array, an operational mode detecting circuit, an address signal input terminal group and a memory cell selecting circuit.
The memory cell array includes memory cells arranged in a plurality of rows and columns. The memory cell array includes a normal memory cell array in which a plurality of normal memory cells are arranged, and a redundant memory cell array in which a plurality of redundant memory cells are arranged for replacing the plurality of normal memory cells.
The operational mode detecting circuit detects that a predetermined operational mode is designated in response to an external instruction.
The address signal input terminal group receives an address signal for selecting a memory cell.
The memory cell selecting circuit independently and successively selects a plurality of normal memory cells and a plurality of redundant memory cells, in response to the address signal in the predetermined operational mode.
Therefore, a main advantage of the present invention is that the acceleration test can be performed for malfunction of the entire memory cell space including the redundant memory cell portion, independent of replacement of a defective memory cell with a redundant memory cell, since the normal memory cell array portion and the redundant memory cell array portion are separated in the memory cell space such that an arbitrary memory cell can be externally selected. This allows testing of the defective memory cell to easily be implemented with high power of detection.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.